Metal-oxide-semiconductor (MOS) devices include source and drain regions, which are often formed by implantations. After the implantations, an anneal step(s) needs to be performed. The annealing step has several functions. First, the ions introduced into the source and drain regions need to be activated to reduce the series' resistances in the source and drain regions. Second, the implantation causes the destruction of the lattice structures in the source and drain regions and hence defects are generated. The annealing step thus has the function of recovering the lattice structure and reducing the number of defects (referred to as defect recovery hereinafter).
FIG. 1 illustrates a cross-sectional view of a MOS device, as implanted, including gate dielectric 12 over substrate 10, gate electrode 14 over gate dielectric 12, lightly-doped source/drain (LDD) regions 16, and deep source/drain regions 18. As implanted, the edges of LDD regions 16 are vertically aligned to the edges of gate electrode 14.
FIG. 2 illustrates the cross-sectional view of a MOS device after the annealing step is performed. There have been various annealing methods explored to achieve the intended effect. Among these methods, an annealing method combining rapid thermal annealing (RTA) and microsecond annealing was commonly used. For example, the RTA is first performed; the wafer is then cooled down to room temperature, followed by a microsecond annealing. The RTA is performed at a relatively lower temperature for a longer time, while the microsecond annealing is performed at a relative higher temperature for a shorter time. The RTA is used for the defect-recovery purpose due to its relatively long time and the microsecond annealing is for improving the activation rate due to its relatively high temperature. However, the RTA, also due to its relatively long time, causes the diffusion of the implanted ions. As a result, as shown in FIG. 2, LDD regions 16 extend into the channel region under gate electrode 14. This causes the difficulty in the short-channel control. The problem becomes even more severe with the increasing down-scaling of integrated circuits, which causes the channel regions of the MOS devices to be increasingly shorter, and hence the diffuse length becomes an increasingly greater portion of the channel length. It is noted that the RTA is important in the annealing. Without the RTA, the defects, as symbolized by the “x” marks in FIG. 1, will remain after the annealing step, with the defects having a high concentration at the interface between substrate 10 and LDD regions 16, and at the interface between substrate 10 and deep source/drain regions 18.
Temperature and duration are two primary factors affecting the results of the annealing and can be manipulated into many combinations in different annealing methods. For example, an annealing method may include several annealing temperatures, each having a duration different from others. Further, many existing annealing methods can be combined. Unfortunately, the results of all these annealing temperatures and durations, when combined, may enhance or degrade each other. Accordingly, the optimum methods (recipes) are still being explored and improved.